Publicación:
División decimal parametrizable usando lenguaje de descripción de hardware

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dc.contributor.authorLopez Botero, Jorge Hernanspa
dc.contributor.authorRestrepo Cardenas, Johansspa
dc.contributor.authorTóbon Gómez, Jorge Enriquespa
dc.date.accessioned2020-02-03 00:00:00
dc.date.accessioned2022-06-17T20:20:21Z
dc.date.available2020-02-03 00:00:00
dc.date.available2022-06-17T20:20:21Z
dc.date.issued2020-02-03
dc.description.abstractEn este trabajo se describe un algoritmo rápido y de alta precisión escrito en el lenguaje de descripción de hardware, VHDL para realizar la división entre dos números decimales, es decir, los números compuestos por una parte entera y una decimal, bajo el esquema de una representación de punto fijo. El algoritmo propuesto no es una aproximación, como se hace en la mayoría de los casos, escogiendo el algoritmo según la necesidad propia, en tiempo o en área de lógica. Para ello, el tamaño de los bits de los operandos se puede ajustar mediante un par de parámetros N y M, según los cuales dependerá la latencia del cálculo. El proyecto se sintetiza finalmente en una matriz de puertas programables o FPGA del tipo SPARTAN 3E de XILINX. spa
dc.description.abstractIn this work we describe a fast and high-precision algorithm written in VHDL Hardware Description Language to perform the division between two_nite decimal numbers, i.e. numbers composed of an integer part and a decimal one, under the scheme of a fixed point representation. The algorithm proposed is not an approximation one as it is usually considered. To do so, the size of the bits of the operands can be tunned by means of a couple of parameters N and M, according to which the latency of the calculation will depend. The project is _nally sinthesized in a _eld programmable gate array or FPGA of the type SPARTAN 3E from XILINX.eng
dc.format.mimetypeapplication/pdfeng
dc.identifier.doi10.24050/reia.v17i33.1318
dc.identifier.eissn2463-0950
dc.identifier.issn1794-1237
dc.identifier.urihttps://repository.eia.edu.co/handle/11190/5081
dc.identifier.urlhttps://doi.org/10.24050/reia.v17i33.1318
dc.language.isoengeng
dc.publisherFondo Editorial EIA - Universidad EIAspa
dc.relation.bitstreamhttps://revistas.eia.edu.co/index.php/reveia/article/download/1318/1290
dc.relation.citationeditionNúm. 33 , Año 2020spa
dc.relation.citationendpage6
dc.relation.citationissue33spa
dc.relation.citationstartpage33016 pp. 1
dc.relation.citationvolume17spa
dc.relation.ispartofjournalRevista EIAspa
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dc.rightsRevista EIA - 2020eng
dc.rights.accessrightsinfo:eu-repo/semantics/openAccesseng
dc.rights.coarhttp://purl.org/coar/access_right/c_abf2eng
dc.rights.creativecommonsEsta obra está bajo una licencia internacional Creative Commons Atribución-NoComercial-SinDerivadas 4.0.eng
dc.rights.urihttps://creativecommons.org/licenses/by-nc-nd/4.0eng
dc.sourcehttps://revistas.eia.edu.co/index.php/reveia/article/view/1318eng
dc.subjectDivisióneng
dc.subjectVHDLeng
dc.subjectFPGAeng
dc.subjectVHDLspa
dc.subjectDivisiónspa
dc.subjectFPGAspa
dc.titleDivisión decimal parametrizable usando lenguaje de descripción de hardwarespa
dc.title.translatedParametric decimal division using hardware description languageeng
dc.typeArtículo de revistaspa
dc.typeJournal articleeng
dc.type.coarhttp://purl.org/coar/resource_type/c_6501eng
dc.type.coarhttp://purl.org/coar/resource_type/c_6501eng
dc.type.coarversionhttp://purl.org/coar/version/c_970fb48d4fbd8a85eng
dc.type.contentTexteng
dc.type.driverinfo:eu-repo/semantics/articleeng
dc.type.redcolhttp://purl.org/redcol/resource_type/ARTREFeng
dc.type.versioninfo:eu-repo/semantics/publishedVersioneng
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